Training Pattern 1 Procedure (Clock Recovery) for 8b/10b Channel Coding Link Rates

Training Pattern 1 Procedure (Clock Recovery) for 8b/10b Channel Coding Link Rates - 3.1 English

DisplayPort 1.4 TX Subsystem Product Guide

Document ID

PG299

Release Date

2022-10-19

Version

3.1 English

Turn off scrambling and set training pattern 1 in the source through direct register writes.
```
SCRAMBLING_DISABLE = 0x01
```
```
TRAINING_PATTERN_SET = 0x01
```
Turn off scrambling and set training pattern 1 in the sink DPCD (0x00102 to 0x00106) through the AUX channel.
Wait for the aux read interval configured in TRAINING_AUX_RD_INTERVAL DPCD register (0x0000E) before reading status registers for all active lanes (0x00202 to 0x00203) through the AUX channel.
If clock recovery failed, check for voltage swing or pre-emphasis level increase requests (0x00206 to 0x00207) and react accordingly.
Run this loop up to five times. If after five iterations this has not succeeded, reduce link speed if at high speed and try again. If already at low speed, training fails.