- Turn off scrambling and set training pattern 2 in the source through direct
SCRAMBLING_DISABLE = 0x01(Not applicable for Training Pattern 4)
Set training pattern to pattern 2, pattern 3, or pattern 4 based on the Sink DPCD capability
- Set proper state for scrambling and set training pattern in the
sink DPCD (
0x00106) through the AUX channel.
- Wait for AUX read interval configured in
TRAINING_AUX_RD_INTERVAL DPCD register (
0x0000E) then read status registers for all active lanes (
0x00203) through the AUX channel.
- Check the channel equalization, symbol lock, and interlane
alignment status bits for all active lanes (
0x00204) through the AUX channel.
- If any of these bits are not set, check for voltage swing or
pre-emphasis level increase requests (
0x00207) and react accordingly.
- Run this loop up to five times. If after five iterations this has not succeeded, reduce link speed if at high speed and Return to the instructions for Training Pattern 1. If already at low speed, training fails.
- Signal the end of training by enabling scrambling and setting
training pattern to
0x00in the Sink device (
0x00102) through the AUX channel.
- On the source side, re-enable scrambling and turn off
TRAINING_PATTERN_SET = 0x00
SCRAMBLING_DISABLE = 0x00