Transmit – Training Issue - 3.1 English

DisplayPort 1.4 TX Subsystem Product Guide

Document ID
PG299
Release Date
2022-10-19
Version
3.1 English

This section contains debugging steps for issues with the clock recovery or channel equalization at sink and if the Training Done is Low.

  1. Try with a working sink such as the DisplayPort Analyzer sink device.
  2. Use a DisplayPort 2.x certified cable. Change the cable and check again.
  3. Put a DisplayPort AUX Analyzer in the Transmit path and check if the various training stages match with those mentioned in Main Link Setup and Management.
  4. Probe the lnk_clk output and check if the SI of the clock is within the Phase Noise mask of the respective GT. The Noise mask requirement is listed in the respective GT documentation.
  5. Check status registers in the Video PHY Controller for Reset done (0x0020) and PLL lock Status (0x0018).