The DisplayPort 1.4 TX Subsystem supports
devices and uses a fabric
8B10B decoder implementation instead of a Xilinx transceiver block
8B10B decoder. For Versal devices,
this results in an additional clock in the subsystem. The following table provides clock
The subsystem supports block automation in IPI for Versal device designs and instantiates the transceiver bridge (PHY) IP and Versal transceiver wizard IP as part of block automation.