AUX Channel Status - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

Document ID
PG300
Release Date
2023-05-18
Version
3.1 English
Table 1. AUX Channel Status
Offset Access Type Description
0x020 RO AUX_REQUEST_IN_PROGRESS. Indicates the receipt of an AUX Channel request

[0] - 1 indicates a request is in progress.

0x024 RO

REQUEST_ERROR_COUNT. Provides a running total of errors detected on inbound AUX Channel requests.

[3:0] - Error count, a write to register address 0x28 clears this counter.

0x028 R/W

REQUEST_COUNT. Provides a running total of the number of AUX requests received.

[7:0] - Total AUX request count, a write to register 0x28 clears this counter.

0x02C WO

HPD_INTERRUPT. Instructs the receiver core to assert an interrupt to the transmitter using the HPD signal. A read from this register always returns 0x0.

[31:16] - HPD_INTERRUPT_LENGTH: Default value is 0. This field defines the length of the HPD pulse. The value should be given in microsecond units. For example for 750 µs, program 750 in the register.

[0] - Set to 1 to send the interrupt through the HPD signal. The HPD signal is brought low for 750 µs to indicate to the source that an interrupt has been requested.

0x030 RO REQUEST_CLOCK_WIDTH. Holds the half period of recovered AUX clock.

[9:0] - Indicates the number of AXI_CLK cycles between sequential edges during the SYNC period of the most recent AUX request.

0x034 RO

REQUEST_COMMAND. Provides the most recent AUX command received.

[3:0] - Provides the command field of the most recently received AUX request.

0x038 RO

REQUEST_ADDRESS. Contains the address field of the most recent AUX request.

[19:0] - The twenty-bit address field from the most recent AUX request transaction is placed in this register. For I2C over AUX transactions, the address range is limited to the seven LSBs.

0x03C RO

REQUEST_LENGTH. The length of the most recent AUX request is written to this register. The length of the AUX request is the value of this register plus one.

[3:0] - Contains the length of the AUX request. Transaction lengths from 1 to 16 bytes are supported. For address only transactions, the value of this register will be 0.

0x040 RC

INTERRUPT_CAUSE. Indicates the cause of a pending host interrupt. A read from this register clears all values. Write operation is illegal and clears the values.

[31] - Cable disconnect/unplug interrupt

[30] - CRC test start interrupt

[29] - MST Act sequence received interrupt

[28] - Interrupt generated when DPCD registers 0x1C0, 0x1C1, and 0x1C2 are written for allocation/de-allocation/partial deletion

[27] - Audio packet FIFO overflow interrupt

[26] - eDP ASSR State change synchronization interrupt bit. It is generated whenever the DisplayPort RX IP synchronizes to the ASSR state change, generated after five status register (SR) symbols after the ASSR state (0 to 1 and 1 to 0) are changed by the DisplayPort source.

[25] - eDP Black Video enable interrupt bit for black video enable set from DPCD

[18] - Training pattern 3 start interrupt

[17] - Training pattern 2 start interrupt

[16] - Training pattern 1 start interrupt

[15] - Bandwidth change interrupt

[14] - TRAINING_DONE: Set to 1 when training is done

[13] - DOWN_REQUEST_BUFFER_READY: Set to 1 indicating availability of Down request

[12] - DOWN_REPLY_BUFFER_READ: Set to 1 for a read event from Down Reply Buffer by upstream source

[11] - VC Payload De-allocated: Set to 0 when de-allocation event occurs in controller

[10] - VC Payload Allocated: Set to 1 when allocation event occurs in controller

[9] - EXT_PKT_RXD: Set to 1 when extension packet is received

[8] - INFO_PKT_RXD: Set to 1 when info packet is received

[7] - Reserved

[6] - VIDEO: Set to 1 when a valid video frame is detected on main link

[5] - Reserved

[4] - TRAINING_LOST: This interrupt is set when the receiver has been trained and subsequently loses clock recovery, symbol lock or inter-lane alignment, in any of the lanes

[3] - VERTICAL_BLANKING: This interrupt is set at the start of the vertical blanking interval as indicated by the VerticalBlanking_Flag in the VB-ID field of the received stream

[2] - NO_VIDEO: Receiver has detected the no-video flags in the VBID field after active video has been received

[1] - POWER_STATE: Transmitter has requested a change in the current power state of the receiver core

[0] - VIDEO_MODE_CHANGE: A change has been detected in the current video mode transmitted on the DisplayPort link as indicated by the MSA fields. The horizontal and vertical resolution parameters are monitored for changes.

0x044 R/W

INTERRUPT_MASK_1: Masks the specified interrupt sources from asserting the axi_init signal. When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up.

[31] - TPS4 Interrupt (DPCD Wr)

[30] - Access TP Lane Set Interrupt (DPCD Wr)

[29] - Access Link Qual Pattern Interrupt (DPCD Wr)

[28] - Access Symbol Error Counter Interrupt (DPCD Rd)

[17] - Video Interrupt - Stream 4

[16] - Vertical Blanking Interrupt - Stream4

[15] - No Video Interrupt - Stream 4

[14] - Mode Change Interrupt - Stream 4

[13] - Info Packet Received - Stream 4

[12] - Ext Packet Received - Stream 4

[11] - Video Interrupt - Stream 3

[10] - Vertical Blanking Interrupt - Stream 3

[9] - No Video Interrupt - Stream 3

[8] - Mode Change Interrupt - Stream 3

[7] - Info Packet Received - Stream 3

[6] - Ext Packet Received - Stream 3

[5] - Video Interrupt - Stream 2

[4] - Vertical Blanking Interrupt - Stream 2

[3] - No Video Interrupt - Stream 2

[2] - Mode Change Interrupt - Stream 2

[1] - Info Packet Received - Stream 2

[0] - Ext Packet Received - Stream 2

0x048 RC

INTERRUPT_CAUSE_1: Indicates the cause of a pending host interrupt. A read from this register clears all values. A write operation would be illegal and would clear all values as well. These bits have the same function as those described in the Interrupt Case register of stream 1. Reserved bits return 0. See offset 0x040 for more description on each interrupt.

[31] - TPS4 Interrupt (DPCD Wr)

[30] - Access TP Lane Set Interrupt (DPCD Wr)

[29] - Access Link Qual Pattern Interrupt (DPCD Wr)

[28] - Access Symbol Error Counter Interrupt (DPCD Rd)

[17] - Video Interrupt - Stream 4

[16] - Vertical Blanking Interrupt - Stream4

[15] - No Video Interrupt - Stream 4

[14] - Mode Change Interrupt - Stream 4

[13] - Info Packet Received - Stream 4

[12] - Ext Packet Received - Stream 4

[11] - Video Interrupt - Stream 3

[10] - Vertical Blanking Interrupt - Stream 3

[9] - No Video Interrupt - Stream 3

[8] - Mode Change Interrupt - Stream 3

[7] - Info Packet Received - Stream 3

[6] - Ext Packet Received - Stream 3

[5] - Video Interrupt - Stream 2

[4] - Vertical Blanking Interrupt - Stream 2

[3] - No Video Interrupt - Stream 2

[2] - Mode Change Interrupt - Stream 2

[1] - Info Packet Received - Stream 2

[0] - Ext Packet Received - Stream 2

0x050 R/W

HSYNC_WIDTH. The display timing generator control logic outputs a fixed length, active-High pulse for the horizontal sync. The timing of this pulse might be controlled by setting this register appropriately. The default value of this register is 0x0F0F.

[15:8] - HSYNC_FRONT_PORCH: Defines the number of video clock cycles to place between the last pixel of active data and the start of the horizontal sync pulse.

[7:0] - HSYNC_PULSE_WIDTH: Specifies the number of clock cycles the horizontal sync pulse is asserted. The vid_hsync signal is High for the specified number of clock cycles.

0x05C R/W

INTERRUPT_MASK_2. Masks the specified interrupt sources from asserting the axi_init signal. When set to a 1, the specified interrupt source is masked. At power up, this register resets to all ones.

[31] - Adaptive Sync SDP interrupt.

[30] - Adaptive Sync vblank interrupt.

0x058 R/W

VSYNC_WIDTH. The display timing generator control logic outputs a fixed length of 63 RX video clocks, active-High pulse for the vertical sync pulse. The timing of this pulse might be controlled by setting this register appropriately. The default value of this register is 0x003F.

[15:0] - VSYNC_WIDTH: Defines the number of RX video clock cycles the vertical sync pulse is asserted. The minimum value to be programmed in this register is 0x003F. User can configure the register based on actual VSYNC duration based on MSA.

0x060 R/W [7:0] - FAST_I2C_DIVIDER. Fast I2C mode clock divider value. Set this value to (AXI4-Lite clock frequency/10) - 1. Valid only for DPCD 1.4.
0x064 R/W [31] - Set to override Training Pattern 1 (TP1) score.

[14:0] - Training pattern1 (TP1) score to override.

0x068 R/W [31] - Set to override the Training Pattern2/3 scores.

[12:0] - Training pattern2/3 (TP2/TP3) score to override.

0x1644 R/W

Read Interval Count Value for 128b/132b training. Default value for this field is 32'd6250000.

[31:0] - CFG_128B132B_AUX_RD_INTERVAL_CNT_VALUE

0x1648 R/W

CDS Sequence Duration Value for 128b/132b training. Default value for this field is 32'd9375000

[31:0] - CFG_128B132B_CDS_SEQ_CNT_VAL

0x164C R/W

PS1 score for 128b/132b training

[15:0] - TPS1 Score

0x1650 R/W

Default FFE PRESET VALUE for 128b/132b training

[31:0] Default FFE PRESET VALUE for 128b/132b so that training starts from this value

0x06C RO

Provides the contents of DPCD registers 0x1C0, 0x1C1, and 0x1C2.

[21:16] - Time slot count

[13:8] - Starting time slot

[5:0] - VC Payload ID

0x070 R/W1C

[31] - Adaptive Sync SDP interrupt and generated when Adaptive Sync SDP packet is received.

[30] - Adaptive Sync vblank interrupt and is generated when the vblank value difference is detected between two consecutive frames.

0x074 R/W

[15:8] - TEST_SINK. Mapped to 00270h DPCD register

[5] - Enable CRC support. The CRC has to be calculated outside the DisplayPort IP and the values have to be provided in 0x078, 0x07C, and 0x080.

[3:0] - CRC change count to be configured by SW

0x078 R/W CRC for Red color
0x07C R/W CRC for Green color
0x080 R/W CRC for Blue color