DPCD Fields - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

Document ID
PG300
Release Date
2023-05-18
Version
3.1 English
Table 1. DPCD Fields
Offset Access Type Description
0x084 R/W LOCAL_EDID_VIDEO. Indicates the presence of EDID information for the video stream.

[0] - Set to 1 to indicate to the transmitter through the DPCD registers that the receiver supports local EDID information.

0x088 R/W LOCAL_EDID_AUDIO. Indicates the presence of EDID information for the audio stream.

[0] - Set to 1 to indicate to the transmitter through the DPCD registers that the receiver supports local EDID information

0x08C R/W REMOTE_COMMAND. General byte for passing remote information to the transmitter.

[7:0] - Remote data byte.

0x090 R/W

DEVICE_SERVICE_IRQ. Indicates DPCD DEVICE_SERVICE_IRQ_VECTOR state.

[4] - Set to 1 to indicate a new DOWN Reply Buffer Message is ready.

[1] - Reflects SINK_SPECIFIC_IRQ state of DPCD 0x201 register. This bit is RO.

[0] - Set to 1 to indicate a new command. Indicates a new command present in the REMOTE_COMMAND register. A Write of 0x1 to this register sets the DPCD register DEVICE_SERVICE_IRQ_VECTOR (0x201), REMOTE_CONTROL_PENDING bit. A write of 0x0 to this register has no effect. Refer to DPCD register section of the standard for more details. Reads from this register reflect the state of DPCD register.

0x094 R/W VIDEO_UNSUPPORTED. DPCD register bit to inform the transmitter that video data is not supported.

[0] - Set to 1 when video data is not supported.

0x098 R/W AUDIO_UNSUPPORTED. DPCD register bit to inform the transmitter that audio data is not supported

[0] - Set to 1 when audio data is not supported.

0x09C R/W

Override LINK_BW_SET. This register can be used to override LINK_BW_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. LINK_BW_SET corresponds to the 00100h and 0x0001h DPCD address space.

  • [4:0] - Link rate override value for DisplayPort Standard v 1.4a/1.2a designs
  • [3:0] - Link rate override value for DisplayPort Standard v1.1a designs
  • 0x6 = 1.62 Gb/s
  • 0xA = 2.7 Gb/s
  • 0x14 = 5.4 Gb/s
  • 0x1E = 8.1 Gb/s
0x0A0 R/W

Override LANE_COUNT_SET. This register can be used to override LANE_COUNT_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. LANE_COUNT_SET corresponds to the 00101h and 0x00002h DPCD address space.

[7] - ENHANCED_FRAME_CAP: Capability override

[6] - TPS3_SUPPORTED: Capability override for DisplayPort Standard v1.4 protocol designs only. Reserved for v1.1a protocol.

[4:0] - Lane count override value (1, 2, or 4 lanes).

0x0A4 R/W

Override TRAINING_PATTERN_SET. This register can be used to override TRAINING_PATTERN_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. TRAINING_PATTERN_SET corresponds to the 00102h DPCD address space.

[23:17] - 128b/132b_TRAINING_AUX_RD_INTERVAL (the values are based on DisplayPort Standard v2.x protocol).

[15:8] - TRAINING_AUX_RD_INTERVAL (the values are based on DisplayPort Standard v1.4 protocol).

[7:6] - SYMBOL ERROR COUNT SEL Override

[5] - SCRAMBLING_DISABLE Override

[4] - RECOVERED_CLOCK_OUT_EN Override

[3:0] - Training Pattern Select

0x0A8 R/W

Override TRAINING_LANE0_SET. This register can be used to override TRAINING_LANE0_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. TRAINING_LANE0_SET corresponds to the 00103h DPCD address space.

[7:6] - Reserved

[5] - MAX_PRE-EMPHASIS_REACHED override

[4:3] - PRE-EMPHASIS_SET override

[2] - MAX_SWING_REACHED override

[1:0] - VOLTAGE SWING SET override

0x0AC R/W Override TRAINING_LANE1_SET. This register can be used to override TRAINING_LANE1_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. Same as Override TRAINING_LANE0_SET. TRAINING_LANE1_SET corresponds to the 00104h DPCD address space.
0x0B0 R/W Override TRAINING_LANE2_SET. This register can be used to override TRAINING_LANE2_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. Same as Override TRAINING_LANE0_SET. TRAINING_LANE2_SET corresponds to the 00105h DPCD address space.
0x0B4 R/W Override TRAINING_LANE3_SET. This register can be used to override TRAINING_LANE3_SET in the DPCD register set. Register 0x0B8 (direct_dpcd_access) must be set to 1 to override DPCD values. Same as Override TRAINING_LANE0_SET. TRAINING_LANE3_SET corresponds to the 00106h DPCD address space.
0x0B8 * R/W Override DPCD Control Register. Setting this register to 0x1 enables AXI/APB write access to DPCD capability structure.
0x0BC R/W

Override DPCD DOWNSPREAD control field. Register 0x0B8 must be set to 1 to override DPCD values.

[0] - MAX_DOWNSPREAD Override. Set to 1'b1 by default.

0x0C0 R/W

Override DPCD LINK_QUAL_LANE0_SET field for DPCD1.4 version only. Register 0x0B8 must be set to 1 to override DPCD values.

[2:0] - LINK_QUAL_LANE0_SET override

0x0C4 R/W

Override DPCD LINK_QUAL_LANE1_SET field for DPCD1.4 version only. Register 0x0B8 must be set to 1 to override DPCD values.

[2:0] - LINK_QUAL_LANE1_SET override

0x0C8 R/W

Override DPCD LINK_QUAL_LANE2_SET field for DPCD1.4 version only. Register 0x0B8 must be set to 1 to override DPCD values.

[2:0] - LINK_QUAL_LANE2_SET override

0x0CC R/W

Override DPCD LINK_QUAL_LANE3_SET field for DPCD1.4 version only. Register 0x0B8 must be set to 1 to override DPCD values.

[2:0] - LINK_QUAL_LANE3_SET override

0x0D0 R/W

[8] - Clears the VCPayload Table contents. This bit is auto cleared.

[7:5] - Unused

[4] - VCPayload Table update bit. SW writes this bit with which the core updates the DPCD register 0x2C0 bit to 1. This bit is used when VC Payload table is controlled through SW

[2] - Set to 1 to override act trigger. Usually, the VCPayload active buffer updates on receiving ACT trigger sequence. This bit can be set when the VC payload table is in SW control. This bit is for advanced users only.

[1] - Set to 1 to enable SW control over VCpayload table. This provides SW write access to offset 0x800-0x8FF. This bit is for advanced users only.

[0] - MST CAPABILITY: Enable or Disable MST capability. Set to 1 to enable MST capability. This bit should be set during the configuration programming stage only.

0x0D4 R/W [6:0] - Sink device count: Recommended to be programmed during initialization of the Sink device. In SST mode, the value should be 1.
0x0D8 R/W [7:0] - DPCD revision. Default is 8'h12
0x0DC R/W [8:0] - AUX EDID defer timeout.
0x0E0 R/W GUID word 0. Allows you to set up GUID if required from host interface. Valid for DPCD1.4 version only.

[31:0] - Lower 4 bytes of GUID DPCD field

0x0E4 R/W GUID word 1. Allows you to set up GUID if required from host interface. Valid for DPCD1.4 version only.

[31:0] - Bytes 4 to 7 of GUID DPCD field

0x0E8 R/W GUID word 2. Allows you to set up GUID if required from host interface. Valid for DPCD1.4 version only.

[31:0] - Bytes 8 to 11 of GUID DPCD field

0x0EC R/W GUID word 3. Allows you to set up GUID if required from host interface. Valid for DPCD1.4 version only.

[31:0] - Bytes 12 to 15 of GUID DPCD field

0x0F0 R/W GUID Override.

[0]: When set to 0x1, the GUID field of the DPCD reflects the data written in GUID Words 0 to 3. Valid for DPCD1.4 version only. When this register is set to 0x1, GUID field of DPCD becomes read only and source-aux writes are NACK-ed.