DisplayPort Overview - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.0 English

The Sink core requires a series of initialization steps before it begins receiving video. These steps include bringing up the Physical Interface (PHY) and setting the internal registers for the proper management of the AUX channel interface.

The Sink policy maker in the example design provides the basic steps for initialization. The following Sink registers are recommended to program after power up:
  • Override LINK_BW_SET
  • Override LANE_COUNT_SET
  • Sink Device Count

These values indicate key DPCD capabilities of the Sink.

The DisplayPort link Hot Plug Detect signal is tied directly to the state of the receiver core enable bit. Until the core is enabled, the receiver does not respond to any AUX transactions or main link video input.

While the Display Timing Generator might be enabled at any time, Xilinx® recommends keeping the DTG disabled until the receiver core policy maker detects the start of active video. This condition can be detected initially through the assertion of the MODE_INTERRUPT which detects the change in the vertical and horizontal resolution values.

Upon receipt of the interrupt, the receiver policy maker should verify the values of the Main Stream Attributes (offset 0x5000x530) to ensure that the requested video mode is within the range supported by the Sink device. If these values are within range, the Display Timing Generator should be enabled to begin passing valid video frames through your data interface.