Link Training - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.0 English

The link training commands are passed from the DPCD register block to the link training function. When set into the link training mode, the functional datapath is blocked, and the link training controller monitors the PHY and detects the specified pattern. Care must be taken to place the Sink core into the proper link training mode before the source begins sending the training pattern. Otherwise, unpredictable results might occur.

The link training process is specified in the VESA DisplayPort Standard (VESA website).

The Main Link for the Sink core drives a stream of video data for you. Using horizontal and vertical sync signals for framing, this user interface matches the industry standard for display controllers and plugs in to existing video streams with little effort. Though the core provides data and control signaling, you are still expected to supply an appropriate clock. This clock can be generated with the use of M and N values provided by the core. Alternatively, you might want to generate a clock by other means. The core underflow protection allows you to use a fast clock to transfer data into a frame buffer.

You can specify one, two, or four pixel-wide data through a register field. The bit width and format is determined from the Main Stream Attributes, which are provided as register fields.
Figure 1. Sink Main Link Datapath

The following figure shows the flow diagram for link training. For details, see the VESA DisplayPort Standard (VESA website).

Figure 2. Link Training States