Pixel Mapping on AXI4-Stream Interface - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.0 English

The output of the DisplayPort 1.4 RX Subsystem is always a quad pixel interface (4PPC). By considering the USER_PIXEL_WIDTH value at the offset address of 0x010 (from now on referred to as USER_PIXEL_WIDTH), 1, 2, or 4PPC from the DisplayPort RX IP is translated (inside DisplayPort Video to AXI4-Stream Bridge) always into 4PPC output from the subsystem. With the output of the subsystem as always 4PPC, the need for an external re-mapper is eliminated, and therefore a significant improvement in resource numbers is achieved.

Note: USER_PIXEL_WIDTH of 4 requires four lanes. USER_PIXEL_WIDTH of 2 requires two lanes. USER_PIXEL_WIDTH of 1 requires one lane. For more information on the relationship between USER_PIXEL_WIDTH and lanes, see the description of offset address 0x010 in Table 1 .

By default, this USER_PIXEL_WIDTH mode is equal to the lane count during subsystem generation. You can override this dynamically. For example, if the driver selects a value of 2 for USER_PIXEL_WIDTH as default, you can change this to 1.

As the input data interface of the subsystem is always 4PPC, valid pixels are available in pixel 0, pixel 1, pixel 2, and pixel 3 position.

The data width of the AXI4-Stream interface depends on different parameters of the core.

Pixel_Width = MAX_BPC × 3

Interface Width = Pixel Width × 4 (because the subsystem's intput data interface is always 4.)

For example, if the system is generated with MAX_BPC equal to 16, the data width of the AXI4-Stream interface is 16 × 4 × 3 which equals 192.