Receiver Core Configuration - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.0 English
Table 1. Receiver Core Configuration
Offset Access Type Description
0x000 R/W LINK_ENABLE. Enable the receiver

1 - Enables the receiver core. Asserts the HPD signal when set.

0x004 R/W

AUX_CLOCK_DIVIDER. Contains the clock divider value for generating the internal 1 MHz clock from the AXI4-Lite host interface clock. The clock divider register provides integer division only and does not support fractional AXI4-Lite clock rates (for example, set to 75 for a 75 MHz AXI4-Lite clock).

[27:24] - Valid values are 0-8. Non-zero value in this field issues defers as per programmed value to DPCD read of LANE0_1_STATUS register. This functionality is needed to extend the clock recovery period from default.

[15:8] - The number of AXI4-Lite clocks (defined by the AXI4-Lite clock name: s_axi_aclk) equivalent to the recommended width of AUX pulse. Allowed values include:0 (default), 8, 16, 24, 32, 40, and 48. Per the DisplayPort protocol specifications, AUX Pulse Width range = 0.4 to 0.6 µs.

[7:0] - Clock divider value

For example, for AXI4-Lite clock of 50 MHz (= 20 ns), the filter width, when set to 24, falls in the allowable range as defined by the protocol spec.

(20 × 24 = 480)

Program a value of 24 in this register.

0x00C R/W

[7] - Mapped ADAPTIVE_SYNC_SDP_SUPPORTED (bit-0 of 02214h DPCD)

[6] - Mapped MSA_TIMING_PAR_IGNORED (bit-6 of 00007h and 02207h DPCD)

[2] - Mapped VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED (bit-3 of 02210h DPCD), Mapped VSC_EXT_VESA_SDP_SUPPORTED (bit-4 of 02210h DPCD) and Mapped VSC_EXT_CTA_SDP_SUPPORTED (bit-6 of 02210h DPCD) bits.

[0] - DTG_ENABLE: Set to 1 to enable the display timing generator in the user interface. The DTG should be disabled when the core detects the no-video pattern on the link.

0x010 R/W

USER_PIXEL_WIDTH. Configures the number of pixels output through the user data interface. The Sink controller programs the pixel width to the active lane count (default). Use quad pixel mode in MST.


  • 1 = Single pixel wide interface. Valid for designs with 1 lane only.
  • 2 = Dual pixel output mode. Valid for designs with 2 lanes only.
  • 4 = Quad pixel output mode. Valid for designs with 4 lanes only.
0x014 R/W INTERRUPT_MASK. Masks the specified interrupt sources from asserting the axi_init signal. When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up.

[31] - Mask for Cable disconnect/unplug interrupt

[30] - CRC test start interrupt

[29] - Mask MST Act sequence received interrupt

[28] - Mask interrupt generated when DPCD registers 0x1C0, 0x1C1 and 0x1C2 are written for allocation/de-allocation/partial deletion

[27] - Audio packet FIFO overflow interrupt

[26] - eDP ASSR State change synchronization interrupt mask bit

[25] - eDP Black Video enable interrupt mask bit

[18] - Training pattern 3 start interrupt

[17] - Training pattern 2 start interrupt

[16] - Training pattern 1 start interrupt

[15] - Bandwidth change interrupt




[11] - VC Payload De-allocated

[10] - VC Payload Allocated

[9] - EXT_PKT_RXD: Set to 1 when extension packet is received

[8] - INFO_PKT_RXD: Set to 1 when info packet is received

[6] - VIDEO: Set to 1 when valid video frame is detected on main link. Video interrupt is set after a delay of eight video frames following a valid scrambler reset character.

[4] - TRAINING_LOST: Training has been lost on any one of the active lanes

[3] - VERTICAL_BLANKING: Start of the vertical blanking interval

[2] - NO_VIDEO: The no-video condition has been detected after active video received

[1] - POWER_STATE: Power state change, DPCD register value 0x00600

[0] - VIDEO_MODE_CHANGE: Resolution change, as detected from the MSA fields

0x018 R/W MISC_CONTROL. Allows the host to instruct the receiver to pass the MSA values through unfiltered.

[2] - When set to 1, I2C DEFERs is sent as AUX DEFERs to the source device.

[1] - When set to 1, the long I2C write data transfers are responded to using DEFER instead of Partial ACKs.

[0] - USE_FILTERED_MSA: When set to 0, this bit disables the filter on the MSA values received by the core. When set to 1, two matching values must be detected for each field of the MSA values before the associated register is updated internally.


[8] - Soft reset control to external HDCP FIFOs.

[7] - AUX Soft Reset: When set, AUX logic resets.

[0] - Soft Video Reset: When set, video logic resets. Reads return zeros.


[7:0] : Maximum line rate. This value is mirrored in 0x2201 DPCD register.