Versal Device Support - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.0 English

The DisplayPort 1.4 RX Subsystem supports Versal® devices and uses a fabric 8B10B decoder implementation instead of a Xilinx transceiver block 8B10B decoder. For Versal devices, this results in an additional clock in the subsystem. The following table provides clock frequency values.

Table 1. Link Clock for Versal Devices
Clock Formula Value
rx_lnk_clk Link Rate/16
  • 506.25 MHz for 8.1 Gb/s
  • 337.50 MHZ for 5.4 Gb/s
  • 168.75 MHz for 2.7 Gb/s
  • 101.25 MHz for 1.62 Gb/s
rx_dec_clk Link Rate/20
  • 405 MHz for 8.1 Gb/s
  • 270 MHZ for 5.4 Gb/s
  • 135 MHz for 2.7 Gb/s
  • 81 MHz for 1.62 Gb/s
The subsystem supports block automation in IPI for Versal device designs and instantiates the transceiver bridge (PHY) IP and Versal transceiver wizard IP as part of block automation.
Note: The rx_lnk_clk and rx_dec_clk are generated from the same clock source. For example, the rx_dec_clk can be generated from the MMCM by taking the rx_lnk_clk as an input clock. For more information, see the Example Design chapter for the VCK190 pass-through example design IPI.