Signal Name | I/O | Description |
---|---|---|
m_axil_awaddr[31:0] | O | This signal is the address for a memory mapped write to the user logic from the host. |
m_axil_awprot[2:0] | O | Protection type. |
m_axil_awvalid | O | The assertion of this signal means there is a valid write request to the address on m_axil_awaddr. |
m_axil_awready | I | Master write address ready. |
m_axil_awuser [54:0] |
O |
m_axil_awuser[11:0] = reserved m_axil_awuser[15:12] = bar id m_axil_awuser[18:16] = reserved m_axil_awuser[30:19] = function number m_axil_awuser[31] = reserved m_axil_awuser[39:32] = bus number m_axil_awuser[42:40] = vf group m_axil_awuser[54:43] = vfg offset |
m_axil_wdata[31:0] | O | Master write data. |
m_axil_wstrb[3:0] | O | Master write strobe. |
m_axil_wvalid | O | Master write valid. |
m_axil_wready | I | Master write ready. |
m_axil_bvalid | I | Master response valid. |
m_axil_bresp[1:0] | I | |
m_axil_bready | O | Master response valid. |
Signal Name | I/O | Description |
---|---|---|
m_axil_araddr[31:0] | O | This signal is the address for a memory mapped read to the user logic from the host. |
m_axil_aruser[54:0] |
O |
m_axil_aruser[11:0] = reserved m_axil_aruser[15:12] = bar id m_axil_aruser[18:16] = reserved m_axil_aruser[30:19] = function number m_axil_aruser[31] = reserved m_axil_aruser[39:32] = bus number m_axil_aruser[42:40] = vf group m_axil_aruser[54:43] = vfg offset |
m_axil_arprot[2:0] | O | Protection type. |
m_axil_arvalid | O | The assertion of this signal means there is a valid read request to the address on m_axil_araddr. |
m_axil_arready | I | Master read address ready. |
m_axil_rdata[31:0] | I | Master read data. |
m_axil_rresp[1:0] | I | Master read response. |
m_axil_rvalid | I | Master read valid. |
m_axil_rready | O | Master read ready. |