Performance and Resource Utilization - 5.0 English

Performance

QDMA performance and detailed analysis is available in AR 71453.

set_property CONFIG.performance_exdes {true} [get_ips qdma_0]

Following are the QDMA register settings recommended by AMD for better performance. Performance numbers can vary based on systems and OS used.

• QDMA_C2H_INT_TIMER_TICK (0xB0C) set to 25. Corresponding to 100 ns (1 tick = 4 ns for 250 MHz user clock)
• C2H trigger mode set to user timer, with counter set to 64 and timer to match round trip latency. Global register for timer should have a value of 30 for 3 μs.
• TX/RX API burst size = 64, ring depth = 2048. The driver should update TX/RX PIDX in batches of 64.
• PCIe MPS = 256 bytes, MRRS >= 512 bytes, Extended Tag Enabled, Relaxed Ordering Enabled
• The driver will update the completion CIDX in batches of 64 to reduce number of MMIO writes before updating the C2H PIDX
• The driver should update the H2C PIDX in batches of 64, and also update for the last descriptor of the scatter gather list.
• C2H context:
  • bypass = 0 (Internal mode)
  • frcd_en = 1
  • qen = 1
  • wbk_en = 1
  • irq_en = irq_arm = int_aggr = 0
• C2H prefetch context:
  • pfch = 1
  • bypass = 0
  • valid = 1
• C2H CMPT context:
  • en_stat_desc = 1
  • en_int = 0 (Poll_mode)
  • int_aggr = 0 (Poll mode)
  • trig_mode = 5
  • counter_idx = corresponding to 64
  • timer_idx = corresponding to 3 μs
  • valid = 1
• H2C context:
  • bypass = 0 (Internal mode)
  • frcd_en = 0
  • fetch_max = 0
  • qen = 1
  • wbk_en = 1
  • wbi_chk = 1
  • wbi_intvl_en = 1
  • irq_en = 0 (Poll mode)
  • irq_arm = 0 (Poll mode)
  • int_aggr = 0 (Poll mode)

For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes.

Performance in Descriptor Bypass Mode

When the design is configured in descriptor bypass mode, all the above setting apply. The following information provides recommendations to improve performance in bypass mode.

• When bypass in h2c_byp_in_st_sdi ports is set, the QDMA IP generates the status write back for every packet. AMD recommends that this port be asserted once in 32 packets or 64 packets. And if there are no more descriptors left then assert h2c_byp_in_st_sdi at the last descriptor. This requirement is per queue basis, and applies to AXI4 (H2C and C2H) bypass transfers and AXI4-Stream H2C transfers.
• For AXI4-Stream C2H Simple bypass mode, the dsc_crdt_in_fence port should be set to 1 for performance reasons. This recommendation assumes the user design already coalesced credits for each queue and sent them to the IP. In internal mode, set the fence bit in the QDMA_C2H_PFCH_CFG_2 (0xA84) register.

Performance Optimization Based on Available Cache/Buffer Size

Prefetch cache size

QDMA prefetch cache size is programmable (16 or 64). When QDMA is configured in an internal mode, the QDMA IP has space for 64 Qs that IP can prefetch the descriptors. If you want to support more than 64 Qs (for example 65 Q's), the engine evicts the least used Q and adds a new Q. This can potentially have a negative effect on the performance for smaller packet sizes and more than 64 Qs. To support more Qs, you can configure the QDMA IP in simple bypass mode and have descriptor cache outside the IP. This way you can manage the descriptor flow.

CPMT data FIFO

QDMA IP has very shallow two deep completion fifo. It will be efficient if you can implement a deeper fifo (512) in your space and feed the output of the fifo to QDMA completion input.

C2h streaming descriptor in FIFO

QDMA IP has a descriptor in fifo which is common for descriptor bypass input and for internal mode. This is 1K deep descriptor fifo. When the fifo fills up, there is back pressure from the IP to your bypass input.

Resources Utilization

For QDMA Resource Utilization, see Resource Use web page.