The Application Example figure shows how the AXI Sideband Formatter Utility IP core is typically used in an IP Integrator design.
Fabric masters "master_0" and "master_1" access the memory controller in
the MPSoC block. The SMMU in the block performs address translation depending on which
master is accessing it. Sideband Formatter instances 0 and 1 are each configured to
perform SMID Insertion, specifying a constant SMID value to distinguish each master. The
SMID value gets inserted into the aruser and awuser signals for each command issued by each master, and
propagate through the SmartConnect to reach the MPSoC. Instance "axi_sideband_util_2"
performs SMID Extraction, retrieving the value from the user signal and transferring it
to the arid or awid
input to the MPSoC block.
In this example, data transfers between the two fabric masters and the
MPSoC through the SmartConnect are also parity-protected. All three Sideband Formatter
instances establish parity endpoints, enveloping the AXI pathways from instances 0 and 1
to instance 2. Parity for the write data channel is generated by instances 0 and 1, and
is checked for parity violations at instance 2. Similarly, read data parity is generated
by instance 2, and checked at each of instance 0 and 1. Typically the w_parity_error output of axi_sideband_util_2 and the r_parity_error outputs of instances 0 and 1 would either be
connected to an interrupt controller or a ChipScope ILA (not shown).