When either of the SI or MI interfaces indicates that it carries parity (enabled), the AXI Sideband Formatter Utility IP core performs parity error detection on the in-bound data channel of each interface where parity is enabled, regardless of whether the opposite interface is also enabled for parity. Parity detection is performed based on the polarity (ODD or EVEN) selected for the interface where the data is received.
If parity is not also being propagated to the opposite interface, the parity bits are stripped and any remaining user-signal value is right-shifted 1 bit-per-byte.
If parity is also enabled on the opposite interface (where the corresponding data channel is out-bound), then in-bound parity information is propagated as-is, including any parity mismatches. If the polarity of the out-bound interface is the same as the in-bound interface (ODD-to-ODD or EVEN-to-EVEN), then parity information is propagated without inversion. If the out-bound polarity is opposite the in-bound interface, then in-bound parity info is inverted and propagated (including any parity mismatches). The AXI Sideband Formatter Utility IP core never generates parity info for in-bound data when the in-bound interface is enabled for parity; it just passes the in-bound parity info through, while checking for errors.
If any parity mismatches are detected in any byte lane of data, the AXI Sideband Formatter
Utility IP
core asserts an error condition during the
valid/ready handshake completion cycle only (not sticky). The error condition is driven
onto the w_parity_error or r_parity_error output signal during the same or subsequent cycle,
depending on whether there is any pipelining configured for the core. Edge-triggered
interrupts can be used to trap parity violations. Connecting to a counter-enable can be
used to determine the number of data beats in which any parity violations occurred.
The assertion of w_parity_error or r_parity_error can optionally be pipelined to improve
timing. Propagation of W-channel or R-channel payload between SI and MI interfaces
remains combinatorial, regardless of error output pipelining.
Write parity detection is masked per deasserted bit of wstrb.
IMPORTANT: Data aggregation during width conversion in the interconnect may produce filler bytes of all-zero DATA and all-zero USER. For that reason, even parity is recommended when propagating across SmartConnect.