LogiCORE IP Facts Table | |
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Core Specifics | |
Supported Device Family 1 |
UltraScale+, UltraScale, 7 series and Zynq®-7000 AP SoC |
Supported User Interfaces | AXI4 and AXI3 |
Resources |
Not Applicable |
Provided with Core | |
Design Files | SystemVerilog |
Example Design | N/A |
Test Bench | N/A |
Constraints File | N/A |
Simulation Model | Unencrypted SystemVerilog |
Supported S/W Driver | N/A |
Tested Design Flows 2 | |
Design Entry | Vivado® Design Suite |
Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
Synthesis | Vivado |
Support | |
Provided by Xilinx® at the Xilinx Support web page | |
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