Port Descriptions - 1.0 English

AXI Sideband Formatter Utility LogiCORE IP Product Guide (PG307)

Document ID
PG307
Release Date
2018-04-04
Version
1.0 English
Revision
Table 1. Signal Interfaces
Interface Signals Dir Width Enablement Description
s_axi {ar,aw}addr I ADDR_WIDTH always Transaction Address
{ar,aw,r,b,w}id - S_ID_WIDTH S_ID_WIDTH>0 AXI ID
{ar,aw,w,r,b}user - S_{AR,AW,W,R,B}USER_WIDTH *USER_WIDTH>0

AXI user signal.

May also carry SMID or parity information.

{r,w}data - DATA_WIDTH always Data payload
other AXI signals - - - as per AMBA® AXI4 specification
m_axi {ar,aw}addr O ADDR_WIDTH always Transaction Address
{ar,aw,r,b,w}id - M_ID_WIDTH M_ID_WIDTH>0

AXI ID

If SMID Extraction enabled, this value is replaced by the SMID constant and sent to the PS fabric interface.

{ar,aw,w,r,b}user - M_{AR,AW,W,R,B}USER_WIDTH *USER_WIDTH>0

AXI user signal.

May also carry SMID or parity information.

{r,w}data - DATA_WIDTH always Data payload
other AXI signals - - - as per AMBA AXI4 spec
(out-of-band) w_parity_error O 1 always

If SI_PARITY=={EVEN,ODD},asserted for 1 cycle while s_axi_wvalid and s_axi_wready if a write parity error has been detected in any byte lane during the current data transfer (not sticky). Error is masked by deasserted wstrb. Output signal may be delayed from detected error condition by one clock cycle per enabled bit of ENABLE_PIPELINING_PARITY.

Error = for any byte lane i: (^s_axi_wdata[i*8 +: 8] ^ s_axi_wuser[i*S_WUSER_BITS_PER_BYTE] ^ (SI_PARITY==ODD)) & s_axi_wstrb[i]

r_parity_error O 1 always

If MI_PARITY=={EVEN,ODD}, asserted for 1 cycle while m_axi_rvalid & m_axi_rready if a read parity error has been detected in any byte lane during the current data transfer (not sticky).

Output signal may be delayed from detected error condition by one clock cycle per enabled bit of ENABLE_PIPELINING_PARITY.

Error = for any byte lane i: ^m_axi_rwdata[i*8 +: 8] ^ m_axi_ruser[i*M_RUSER_BITS_PER_BYTE] ^ (MI_PARITY==ODD)

w_parity_error_injection I 1 always Force w_parity_error output high while s_axi_wvalid & s_axi_wready are asserted regardless of error detection.

Output signal may be delayed from valid/ready handshake cycle by one clock cycle per enabled bit of ENABLE_PIPELINING_PARITY.

r_parity_error_injection I 1 always Force r_parity_error output high while m_axi_rvalid & m_axi_rready are asserted regardless of error detection.

Output signal may be delayed from valid/ready handshake cycle by one clock cycle per enabled bit of ENABLE_PIPELINING_PARITY.

aclk aclk I 1 always Clock for internal state.
aclken aclken I 1 always Clock enable for internal state; connection optional (default 1)
aresetn aresetn I 1 always

Active-Low reset for internal state; connection optional (default 1).

This IP may propagate AXI handshake signals combinatorially and without gating handshake outputs with aresetn; in-bound handshakes asserted during reset may cause unpredictable output transfers.