SMID for MPSoC SMMU - 1.0 English

In Zynq® UltraScale+™ MPSoC, the processor SMMU performs address translation based on a System Management ID tag (SMID). See the Zynq UltraScale+ Device Technical Reference Manual (UG1085). The SMID identifies the master device that is accessing one of the slave devices in the processor block via the SMMU. SMID values are normally communicated among masters and slaves within the Processing System hard-block. AXI interfaces of the fabric IP do not natively communicate SMID information. However, SMID values can be transported across the fabric as sideband information as part of the AXI awuser or aruser signal. You can connect the AXI Sideband Formatter Utility IP core along AXI pathways in the fabric to insert and extract SMID values so that fabric masters can take advantage of SMMU address translation when accessing PS block slaves.

For each fabric master that accesses the PS block, you can insert an AXI Sideband Formatter Utility IP core between the master's AXI interface and the fabric interconnect. You then configure the IP to insert an SMID value for that master into the AXI awuser or aruser signal. You can connect another AXI Sideband Formatter IP core between the fabric interconnect and one of the AXI fabric slave interfaces of the Zynq UltraScale+ MPSoC Processing System core. You then configure this slave-side IP to extract the SMID value and pass it to the PS block in the format expected by the SMMU.