AES Channel Status (0x50-0x64) - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

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These six registers together allow the user to specify the 192-bit channel status information that is inserted over the audio block. These registers give the value in order of LSB to MSB. The register 0x50 should have the bits [31:0] of 192-bit channel status, while register 0x64 should have the bits [191:160].

Table 1. Receiver AES Channel Status (0x50-0x64)
Bit Default Value Access Type Description
31:0 0 R/W 32-bit AES Value: 32-bit AES channel status value.