There are three possible clock inputs available. Ensure that a proper
aud_clk is supplied so that the correct SCLK can be generated by the IP.
The audio clock is typically an integer multiple of 128×Fs and is decided by the DAC/ADC being
used. To minimize jitter, use a very stable clock source to generate the audio clock.
LRCLK is also generated by the IP in master mode. LRCLK edges coincide with the falling edge of SCLK following I2S protocol. Typically LR clock frequency is SCLK frequency divided by (2 * I2S data width). In cases where Left/Right justification is selected or when 32-bit LRCLK is selected, LR clock frequency is SCLK frequency divided by (2*32).
|s_axi_ctrl_aclk||Control interface clock|
|s_axis_aud_aclk||AXIS streaming clock|
|m_axis_aud_aclk||AXIS streaming clock|
|aud_aclk||A reference audio clock which is an integer multiple of Fs (typically 128×Fs, 384×Fs, etc.)|