Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
For more information, see Clocking.Clock Management
It is advisable to have the audio clock generated from a stable source for minimal jitter. If the jitter is of low importance, a MMCM can be used to generate the audio clock.Clock Placement
Audio clock, if supplied from an external source, should be connected to a clock capable I/O so that it can be used by the FPGA fabric.Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.