This register lets you enable/disable the core.
|Bit||Default Value||Access Type||Description|
|16||0||WO||Latch AES Channel Status: Program this bit to latch the AES channel status bits from the registers. This latched value is then put onto the AXIS interface. This register is auto cleared.|
|3||0x0||RO||Selected 32-bit LR clock mode|
|2||0x0||R/W||Valid when bit 1 is set. Selects left/right justification:
|1||0x0||R/W||Enable Left/Right Justification|
|0||0x0||R/W||Enable: Setting this bit to ‘1’ enables the core operations. Setting this bit to ‘0’ disables the core operations.|