Example Design - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

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1.0 English

This chapter contains information about the example design provided in the Vivado® Design Suite. The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown below. This includes the Clocking Wizard and the Register configuration modules. The available Example Design is shown in the following table.

Table 1. Example Design
Topology Hardware Processor
Loopback TX-RX N/A - Simulation only ATG
Note: Behavior of this IP is also shown in the HDMI Pass-Through +I2S Audio Example Design documented in the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235).
Figure 1. Core Example Design
Note: The I2S Connection from Transmitter to Receiver is an external connection which is implemented in the test-bench of the design for simulation purposes. Practically, the connection has to be made outside the board.

The core example design is a simulation-only design; it cannot be validated on the board. This example design demonstrates transactions on the AXI4-Lite and AXI4-Stream interfaces of the DUT.

Clock generator
A clocking wizard is used to generate the clocks for the example design. It generates the aud_clk, AXI4-Lite clock, and the AXI4-Stream clock. The example design is held in reset until the MMCM is locked.
Axi Traffic Generator (ATG)
The ATGs are used to program the I2S IPs. The ATGs start the configuration process as soon as the MMCM is locked.
I2S Transmitter
This module receives the audio data and sends it over to the I2S bus that is connected to the I2S receiver.
I2S Receiver
This module receives the I2S data and outputs it on the AXIS interface.