I2S Transmitter Register Space - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2021-11-10
Version
1.0 English
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.
Table 1. Register Address Space
Address (hex) Register Name
0x00 Core Version: Returns the core major and minor versions
0x04 Core Configuration: Returns the core configuration details
0x08 Core Control: Register to enable/disable the core
0x0C Validity Register: Validates the incoming sample word
0x10 Interrupt Control: Interrupts the enable/disable register
0x14 Interrupt Status: Interrupts the Status register
0x20 I2S Timing Control: Register to program the SCK divider value
0x30 Channel 0/1 Control: Channel 0/1 control register
0x34 Channel 2/3 Control: Channel 2/3 control register
0x38 Channel 4/5 Control: Channel 4/5 control register
0x3C Channel 6/7 Control: Channel 6/7 control register
0x50 AES Channel Status 0: Register that returns the LSB 32-bit of the AES Channel Status
0x54 AES Channel Status 1: Register that returns the next LSB 32-bit of the AES Channel Status
0x58 AES Channel Status 2: Register that returns the 32-bit of the AES Channel Status
0x5C AES Channel Status 3: Register that returns the 32-bit of the AES Channel Status
0x60 AES Channel Status 4: Register that returns the 32-bit of the AES Channel Status
0x64 AES Channel Status 5: Register that returns the MSB 32-bit of the AES Channel Status