Core Specifics |
Supported Device Family
1
|
Versal®
ACAP,
UltraScale+™
,
UltraScale™
,
Zynq®-7000 SoC, 7 series,
Zynq®
UltraScale+™ MPSoC. |
Supported User Interfaces |
AXI4-Lite, AXI4-Stream, AXI4
|
Resources |
Performance and Resource Use web page for
transmitter and Performance and Resource Use web page for
receiver. |
Provided with
Core
|
Design Files |
SystemVerilog |
Example Design |
SystemVerilog |
Test Bench |
SystemVerilog |
Constraints File |
Delivered at the time of IP generation |
Simulation Model |
Source HDL |
Supported S/W Driver
2
|
Standalone |
Tested Design Flows
3
|
Design Entry |
Vivado® Design Suite, Vivado
IP integrator |
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Records: 70288 (RX), 70699 (TX) |
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Xilinx Support
web page
|
- For a complete list of supported devices, see the Vivado IP
catalog.
- Standalone driver details can be found in the
Vitis™
software platform directory
(<install_directory>/vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
Linux OS and driver support information is available from the Xilinx Wiki
page.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|