Interrupt Control Register (0x10) - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

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This register determines the interrupts sources in the Interrupt Status register that are allowed to generate an interrupt. Writing a ‘1’ to a bit enables the corresponding interrupt.

Table 1. Receiver Interrupt Control Register (0x10)
Bit Default Value Access Type Description
31 0 R/W Global Interrupt Enable: Enables the global interrupt.
30:2     Reserved
1 0 R/W Overflow Interrupt Enable: Enables the overflow interrupt.
0 0 R/W AES Block Completed Interrupt Enable: Enables the AES block completed interrupt.