Audio Control Register (0x18) - 2.0 English

UHD SDI Audio LogiCORE IP Product Guide (PG309)
Document ID
PG309
Release Date
2021-12-01
Version
2.0 English
Table 1. Audio Control Register - UHD-SDI Audio (Extract)
Bit Field Name Access Type Default Value Description
31:30 reserved N/A 0 Reserved
29 Ignore_clk_phase R/W 0 This bit when set to 1, ignores the clock phase information while outputting data
28:20 reserved N/A 0 Reserved
19:16 aes_chan_pair R/W 0 This signal selects the channel pair from which 192-bit AES channel status need to be extracted
  • 0 – Channel Pair 1 (Channel 1 & 2)
  • 1 – Channel Pair 2 (Channel 3 & 4)

through

  • 15 – Channel Pair 16 (Channel 31 & 32)
15:0 reserved N/A 0 Reserved