Clocking - 2.0 English

UHD SDI Audio LogiCORE IP Product Guide (PG309)

Document ID
PG309
Release Date
2021-12-01
Version
2.0 English
The list of clocks in UHD-SDI Audio (Embed).
s_axi_aclk
This is the processor domain clock. AXI4-Lite interface works on this clock.
s_axis_clk
This is the AXI4-Stream interface clock. This should be greater than 512 times the audio sampling rate.
sdi_embed_clk
This is the video domain clock. It is 74.25 MHz or 74.175 MHz during HD SDI, 148.5 MHz or 148.35 MHz during SD/3G/6G SDI and 297 MHz during 12G SDI mode. This is the same clock connected to sdi_tx_clk of the Xilinx® UHD-SDI TX Subsystem.
The list of clocks in UHD-SDI Audio (Extract).
s_axi_aclk
This is the processor domain clock. AXI4-Lite interface works on this clock.
m_axis_clk
This is the AXI4-Stream interface clock. This should be greater than 512 times the audio sampling rate.
sdi_extract_clk
This is the video domain clock. It is 74.25 MHz or 74.175 MHz during HD SDI, 148.5 MHz or 148.35 MHz during SD/3G/6G SDI and 297 MHz during 12G SDI mode. This is the same clock connected to sdi_rx_clk of the Xilinx UHD-SDI RX Subsystem.