Perform the following general checks:
- Ensure that all timing constraints were met during implementation.
- Verify that all clocks are connected with expected frequencies.
- Verify that all resets are connected with expected polarities.
Ensure that core is generated with expected configuration (Audio function, SDI line rate, Maximum audio channels, Axi4-Lite enable, etc) by reading the “GUI Parameters” register (Offset - 0xFC).
AXI4-Stream Slave Interface
Ensure that audio samples are strictly distributed as per the sample rate. One sample per each channel per one audio clock period (48 KHz, 44.1 KHz, 32 KHz).
SDI Transmitter Ancillary Data Control
Perform the following checks.
- The Audio Embedder receives video data streams from SDI Transmitter, embeds audio and transmits the audio embedded video data streams back to the SDI Transmitter core.
- The Xilinx® SDI Transmitter has the provision to use the video data streams or audio embedded video data streams (ancillary data).
- If Audio Embedder is embedding the audio data and the audio data is not visible on the SDI link, ensure that the SDI Transmitter is configured to use the ancillary data path.
After all the configuration is done, if the UHD-SDI Audio IP core is not
working as expected, ensure that core is out of reset by probing