When designing with custom or non-production IP, it is common to encounter system malfunctions caused by AXI protocol violations. Xilinx® AXI IP cores, including RAMA, do not contain any logic to guard against AXI protocol violations incurred by IP cores to which they are connected.
One of the most common symptoms of an AXI protocol violation in a system is an apparent lock-up of a connected core. When such a lock-up condition occurs, it often appears that an AXI channel transfer (valid/ready handshake) completes on one interface of the RAMA, but the resultant transfer is never issued on the expected output interface. Other possible symptoms include output transfers that appear to violate AXI transaction ordering rules.