AXI3 RAMA Master Interface I/O Signals - 1.1 English

RAMA 1.1 LogiCORE IP Product Guide (PG310)

Document ID
PG310
Release Date
2021-01-21
Version
1.1 English
Table 1. RAMA Master Interface I/O Signals
Port Name I/O Description
M_AXI_AWID[5:0] O Write Address Channel Transaction ID
M_AXI_AWADDR[32:0] O Write Address Channel Address
M_AXI_AWLEN[7:0] O Write Address Channel Burst Length Code (0–255)
M_AXI_AWSIZE[2:0] O Write Address Channel Transfer Size Code (0–7)
M_AXI_AWBURST[1:0] O Write Address Channel Burst Type (0–2)
M_AXI_AWVALID O Write Address Channel Valid
M_AXI_AWREADY I Write Address Channel Ready

Input Required

M_AXI_WDATA[255:0] O Write Data Channel Data
M_AXI_WSTRB[31:0] O Write Data Channel Data Byte Strobes
M_AXI_WLAST O Write Data Channel Last Data Beat
M_AXI_WVALID O Write Data Channel Valid
M_AXI_WREADY I Write Data Channel Ready

Input Required

M_AXI_BID[5:0] I Write Response Channel Transaction ID

Input Required

M_AXI_BRESP[1:0] I Write Response Channel Response Code (0–3)

Default = 0

M_AXI_BVALID I Write Response Channel Valid

Input Required

M_AXI_BREADY O Write Response Channel Ready
M_AXI_ARID[5:0] O Read Address Channel Transaction ID
M_AXI_ARADDR[32:0] O Read Address Channel Address
M_AXI_ARLEN[7:0] O Read Address Channel Burst Length Code (0–255)
M_AXI_ARSIZE[2:0] O Read Address Channel Transfer Size Code (0–7)
M_AXI_ARBURST[1:0] O Read Address Channel Burst Type (0–2)
M_AXI_ARVALID O Read Address Channel Valid
M_AXI_ARREADY I Read Address Channel Ready

Input Required

M_AXI_RID[5:0] I Read Data Channel Transaction ID
M_AXI_RDATA[255:0] I Read Data Channel Data

Input Required

M_AXI_RRESP[1:0] I Read Data Channel Response Code (0–3)

Default = 0

M_AXI_RLAST I Read Data Channel Last Data Beat

Input Required

M_AXI_RVALID I Read Data Channel Valid

Input Required

M_AXI_RREADY O Read Data Channel Ready