| Port Name | I/O | Description |
|---|---|---|
| S_AXI_AWID | I | Write Address Channel Transaction ID Default = 0 |
| S_AXI_AWADDR[32:0] | I | Write Address Channel Address Input Required |
| S_AXI_AWLEN[7:0] | I | Write Address Channel Burst Length (0-255) Default = 0 |
| S_AXI_AWSIZE[2:0] | I | Write Address Channel Transfer Size Code (0–7) Input Required |
| S_AXI_AWBURST[1:0] | I | Write Address Channel Burst Type Code (0-2) Input Required |
| S_AXI_AWVALID | I | Write Address Channel Valid Input Required |
| S_AXI_AWREADY | O | Write Address Channel Ready |
| S_AXI_WDATA[255:0] | I | Write Data Channel Data Input Required |
| S_AXI_WSTRB[31:0] | I | Write Data Channel Byte Strobes Default = All ones |
| S_AXI_WLAST | O | Write Data Channel Last Data Beat Default = 0 |
| S_AXI_WVALID | I | Write Data Channel Valid Input Required |
| S_AXI_WREADY | O | Write Data Channel Ready |
| S_AXI_BID | O | Write Response Channel Transaction ID |
| S_AXI_BRESP[1:0] | O | Write Response Channel Response Code (0–3) |
| S_AXI_BVALID | O | Write Response Channel Valid |
| S_AXI_BREADY | I | Write Response Channel Ready Input Required |
| S_AXI_ARID | O | Read Address Channel Transaction ID Default = 0 |
| S_AXI_ARADDR[32:0] | I | Read Address Channel Address Input Required |
| S_AXI_ARLEN[7:0] | I | Read Address Channel Burst Length Code (0–255) Default = 0 |
| S_AXI_ARSIZE[2:0] | I | Read Address Channel Transfer Size Code (0–7) Input Required |
| S_AXI_ARBURST[1:0] | I | Read Address Channel Burst Type (0–2) Input Required |
| S_AXI_ARVALID | I | Read Address Channel Valid Input Required |
| S_AXI_ARREADY | O | Read Address Channel Ready |
| S_AXI_RID | O | Read Data Channel Transaction ID |
| S_AXI_RDATA[255:0] | O | Read Data Channel Data |
| S_AXI_RRESP[1:0] | O | Read Data Channel Response Code (0-3) |
| S_AXI_RLAST | O | Read Data Channel Last Data Beat |
| S_AXI_RVALID | O | Read Data Channel Valid |
| S_AXI_RREADY | I | Read Data Channel Ready Input Required |