The RAMA IP provides performance improvements in HBM random memory access efficiency in applications where memory space is greater than 256 MB. See AXI Thread IDs for the additional conditions required to maximize the RAMA IP’s performance improvement.
The RAMA IP can additionally improve performance in applications where multiple masters share access to HBM pseudo-channels. The memory interleaving option can be used to stripe data across more pseudo-channels than required (in terms of memory capacity) increasing the number of pseudo-channels used. This increases the total memory bandwidth available and in turn increases the performance.
This feature can also be used to limit congestion on an individual pseudo-channel. Consider a case where long transactions occur from a particular AXI master. These long transactions can be split across multiple pseudo-channels balancing the load on the HBM Subsystem and preventing instantaneous congestion on a single pseudo-channel.