A single clock domain,
AXI_ACLK, is used.
The design has been verified for clock frequencies up to 450 MHz, which is the nominal
frequency for the HBM Subsystem AXI switch (see Features section for lower speed grades). Both
interfaces, slave and master, must operate in the same clocking domain. For adapting clock
domain and data width to RAMA requirements, see the
SmartConnect LogiCORE IP Product Guide (PG247).Note: The
SmartConnect IP should not be used between the RAMA IP and the HBM Subsystem IP as the AXI
ID multi-threading approach used in RAMA will cause the SmartConnect IP to consume large
amounts of logic resources.
Any required soft switching should take place in front of the slave port of the RAMA IP.