Core Overview - 1.1 English

RAMA 1.1 LogiCORE IP Product Guide (PG310)

Document ID
PG310
Release Date
2021-01-21
Version
1.1 English

The high bandwidth memory (HBM) subsystem in Virtex® UltraScale+™ devices performs well in applications where sequential data access is required. However, for applications requiring random data access, performance can vary significantly depending on the application requirements (for example, the ratio of read and write operations, minimum data word size, and memory size). The RAMA IP addresses such issues by significantly improving memory access efficiency in cases where the required memory exceeds 256 MB (one HBM pseudo-channel).

The following figure describes the connections between programmable logic masters and HBM.

Figure 1. HBM Two Stack Configuration

In the most common use case, where the master's transactions use a single AXI ID, the hardened AXI3 Interconnect switch, used to connect masters to the HBM, has the limitation that any master can have an outstanding transaction with only one slave. This limitation can significantly reduce data bandwidth when masters frequently switch between slaves. This effect is greater for read access, due to longer response times.

The RAMA IP uses AXI ID substitution and response reordering to provide memory access performance improvements for random data access in all cases where more than one pseudo-channel of the HBM stack is accessed by a single master. The greatest advantage is achieved for read intensive data accesses.