Example Design RAMA Configuration Limitations - 1.1 English

RAMA 1.1 LogiCORE IP Product Guide (PG310)
Document ID
PG310
Release Date
2021-01-21
Version
1.1 English
Not all RAMA configurations are supported in the example design. An error will be issued for the following cases:
  • RAMA AXI input address width of less than 30 bits (1 GB addressing capability is required)
  • Memory interleaving configured across more than 16 HBM pseudo-channels (Only a single HBM stack is enabled giving a maximum of 16 HBM pseudo-channels)