The main components of the example design are:
- An AXI traffic generator used to generate randomly distributed traffic (across 1 GB of HBM address space)
- An AXI Monitor used to capture the resultant bandwidth achieved
- An instance of the HBM IP with a single stack enabled (that is 4 GB)
Searching the simulation log will show an output from the AXI Performance Monitor such
as:
# ** Note: $finish : ../../../../imports/example_my_ip.v(126)
# Time: 59955215 ps Iteration: 0 Instance: /example_my_ip
# =========================================================
# >>>>>> SRC_ID 0 :: AXI_PMON :: BW ANALYSIS >>>>>>
# =========================================================
# AXI Clock Period = 2222 ps
# Min Write Latency = 33 axi clock cycles
# Max Write Latency = 44 axi clock cycles
# Avg Write Latency = 41 axi clock cycles
# Actual Achieved Write Bandwidth = 10338.435136 MBps
# ***************************************************
# Min Read Latency = 91 axi clock cycles
# Max Read Latency = 280 axi clock cycles
# Avg Read Latency = 174 axi clock cycles
# Actual Achieved Read Bandwidth = 11018.699422 MBps
# =========================================================