- Performance improvement for random access memory, measured relative to the
design without RAMA IP. The following table uses an
improvement multiplier rather than the efficiency figure. For example, for 64 B read only
transactions, the measured bandwidth without RAMA is 4225 MB/s, while with RAMA it is 40730
MB/s, thus an almost 10 times improvement in bandwidth.
Table 1. Random Access Performance Improvement
| Access Type |
32 B |
64 B |
128 B |
256 B |
512 B |
| Read Only |
10 |
10 |
5 |
3 |
2 |
| Write Only |
2 |
2 |
1.5 |
1 |
1 |
| Read/Write |
3 |
3 |
2 |
1 |
1 |
-
AXI4 interface on user’s side,
AXI3 interface on HBM side (256 bits). AXI3 is used by the hardened AXI3 Interconnect Switch to access HBM.
- Operating clock frequency (single clock domain): 450 MHz (420 MHz for -1
parts and 350 MHz for -2LV parts).
- Address width: Up to 33 bits for 4 GB HBM stack size and up to 34 bits for
8 GB HBM stack size. For more information, see
AXI High Bandwidth Controller LogiCORE IP Product
Guide (PG276).
- ID Width: Up to 6 bits.