2x16 Component Interface (Flipped) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The integrated DDRMC can also be configured as two independent DDR interfaces of 16, or 32 data bits each. This section describes the Flipped 2x16 LPDDR4/4X interface.

Figure 1. Connections for a 2x16 LPDDR4/4x Interface

Nibble utilization for 2x16 interface using a x32 component in the flipped configuration is shown in the following figure. DQ indicates data nibbles, AC indicates Address/Command/Control nibbles, sys_clk indicates a nibble comprising the Reference Clock pair, RESET_n, and ALERT_n signals. For a 1x16 interface nibbles 4, 5, 6, 7, and 8 in the second Bank and nibbles 2, 3, 6, and 7 in the third Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble utilization for 2x16 component interface (Flipped)