AXI Configuration Assumptions - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Each NMU and NSU has a configurable data width to allow you to define the interface width of the NMU or NSU.

For the NMU AXI-MM interface, the AxSize of the master is defined by the AxSize input of the transaction.

For the the NSU AXI-MM interface, the AxSize of the slave is implied with the following assumptions:

  • For modifiable transactions, the AxSize of the slave must be equal to the interface width of the slave. This defines the NSU packing width in modifiable transactions.
  • For non-modifiable transactions, the slave must support the AxSize of the master or smaller. This is because the NSU would either narrow transfer or downsize the transfer from the AxSize of the Master to the Slave interface.
  • AxSize of the DDRMC is fixed at 4 (128-bit). The NMU always upsizes or downsizes into the AxSize of 4 (128-bit) for DDR transactions.
For AXI4-Stream:
  • Only PL and AI Engine interfaces use AXI-S.
  • TDEST signal support for soft interconnect.