AXI Conversion Overview - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

For a request or response transaction, AXI information including AxSize, AxLen, AxBurst, AxCache[1] (modifiable/non-modifiable transaction), AxLock (Normal/Exclusive access), and AxAddr, are carried along the transaction to/from the NoC Master, the NMU, the NoC channel, the NSU and the NoC Slave. The NoC header always carries consistent AXI information that describes the Read/Write request it is carrying. Because the NoC channel has a128-bit interface width, an AXI request is always converted (downsized or upsized) from the AxSize of Master to match the AxSize of the NoC (128-bit) for a modifiable transaction. For a non-modifiable transaction, the AXI request could go through narrow-transfer or forced-downsize.

A request could be chopped by either a programmable chop (REG_CHOPSIZE) by the NMU or in the case of AXI downsize in the NSU, a chop may be required to keep the AxLen less than 256 for AXI4.

The following figure shows the logic view of the NMU and the NSU for AXI conversion. There are upsize and downsize blocks in both request and response directions. In addition, the NMU/NSU supports full transfer and narrow-transfer requests/responses. The NSU performs narrow transfer or full transfer based on AxCache[1] (modifiable/non-modifiable), and the AxSize of the master, the NoC, and the slave.

Figure 1. AXI Conversion Overview