AMD Versal™ architecture and interconnect is consistent with the AMBA® AXI standard, and as such, each transaction is accompanied by an AXI ID. The master may use a single AXI ID for all its transactions, or may issue different transactions with different IDs. Since the same AXI ID is returned with the transaction response, it can be used by the master to forward the response to the appropriate internal destination if there is more than one. An example of the use of the AXI ID within a complex master is an 8-channel DMA. For data transfers eight different AXI IDs are used, one per channel, and an additional eight AXI IDs are used, one per channel, for the descriptor access. By inspecting the AXI ID in the response, the DMA logic knows how to handle the arriving response.
An important aspect of AXI ID is that transactions which have the same AXI ID must be returned in the same order they were issued, while transactions with different IDs may be returned in any order. Suppose the master is a simple function with a single thread of data access. Using a single ID ensures that transactions are returned in the order issued. Using multiple IDs may cause transactions to be returned out of order, and may require special handling in the master to understand the sequence, and possibly reorder the arriving responses. It may therefore be preferable to use a single ID in such cases. However, in most cases better performance is achieved using multiple IDs. It is therefore advisable to assess the possible performance improvement against the extra design complexity in the master.
- All transactions use the same AXI ID for a maximum OT of 64. This is assuming a single master via NoC NMU).
- Each transaction uses a unique ID for a max OT of four.
These limits are independent for the read and write channels.