Accessing Error Reporting and Logging Registers - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2023-11-01
Version
1.0 English

Table 1 shows the NPI identifier for each pseudo channel of each HBM controller. In order to access a register for a pseudo channel of an HBM controller, use the corresponding NPI ID to identify the appropriate register module from Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019). For example, to read the Interrupt Status Register (REG_ISR) for pseudo channel 0 of HBM controller 0, the NPI ID is mentioned as MC_12 in the table. REG_ISR for the pseudo channel 0 falls in the HBMMC_NA0 register module. Thus, you need to specifically check HBMMC_NA0_12 to determine the address of this register. As mentioned in Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019), the required address is 0xF6EFE010.

The error logging registers for HBM are in the NPI domain and a part of the upper SLR PMC. To access these registers from the NoC, the appropriate PMC alias address offset must be used, as described in the Versal Adaptive SoC Technical Reference Manual (AM011). All PMC addresses are modified if the access is from the NoC. Each SLR has an addressing alias required to access these registers. The HBM registers fall in SLR1 and hence the user needs to use the PMC address alias accordingly. The starting address for PMC1_alias is 0x001_0800_0000. To continue with the example mentioned above, to access REG_ISR from the HBMMC_NA0_12 register module through NoC, the user needs to use the following equation to calculate the new address:

New Register Address = 0x001_0800_0000 - 0xF000_0000 + register base address

Thus, the new address for REG_ISR will be 0x001_0EEF_E010.

For lists of addresses and NoC Site locations, see AR 000035076.