Address Mapping - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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Address mapping allows the mapping of incoming AXI address to DRAM rows, banks, bank groups and columns. It is important to understand the physical address space of the HBM as well as the address mapping options to achieve the most efficient performance for the design. The following table defines the physical address map for 4H and 8H devices:

Table 1. Address Map: 4H and 8H
HBM Arrangement 4H Device (Single Stack) 8H Device (Dual Stack) 8H Device (Dual Stack)
Density per Channel 8 Gb 8 Gb 16 Gb
Density per Pseudo Channel 4 Gb 4 Gb 8 Gb
Row Address RA[14:0] RA[13:0] RA[14:0]
Column Address CA[5:1] CA[5:1] CA[5:1]
Bank Group Address BA[3:0] SID, BA[3:0] SID, BA[3:0]
Bank Arrangement 16 Banks

4 Bank Groups with 4 Banks

32 Banks

8 Bank Groups with 4 Banks

32 Banks

8 Bank Groups with 4 Banks

Total User Address Bits 24 24 25

The total address space of a 4H device is 34 bits and for an 8H device it is either 34 or 35 bits depending on the size per stack of the device. The following table describes the AXI addressing for these devices.

Table 2. AXI Addressing
HBM Arrangement 4H Device (Single Stack) 8H Device (Dual Stack) 8H Device (Dual Stack)
Total Address Bits 34 total as 33:0 34 total as 33:0 35 total as 34:0
Stack Select: 0=Left, 1=Right 33 33 34
Destination AXI Port: 0-15 32:29 32:29 33:30
HBM Address Bits 28:5 28:5 29:5
Unused Address Bits 4:0 4:0 4:0

HBM operation closely follows that of traditional volatile memories and is specifically similar to DDR4. The basics of protocol operation dictate the resulting efficiency when accessing the memory array, and this must be a significant consideration along with the user AXI access pattern and how the user logic is driving the AXI channels during operation.

Like DDR4, HBM uses the concept of banks and bank groups for the memory and leveraging these concepts is how to achieve a highly efficient array access pattern. 4H devices have a total of 16 banks, arranged as four bank groups each with four banks. 8H devices have 32 banks, arranged as eight bank groups with four Banks.

The HBM supports one active row address per bank. Protocol access times between banks in different bank groups are lower than when accessing banks within the same bank group, and the currently active bow within a bank must be precharged before a different row within that bank can be activated. When a row is activated within a bank, it is recommended to perform multiple column accesses within that row before changing the row. Doing this is considered to result in a high page hit rate, which means higher efficiency.

By default, the address mapping is set to Row Bank Column map with the Bank Group Interleave option enabled. With these default settings, the highest order address bits are the row address (RAx) bits, of which only one row address per bank can be active at a time. The middle address bits are the Bank address bits, which are displayed as SID for stack ID, BGx for bank group and BAx for bank addresses. The next address range is the volumn address bits which are displayed as CAx, and these are accessed by write and read commands. The lowest configurable bit is a BGx bit which enables bank group interleaving.

The Bank Group Interleave option means that BG0, the least significant bit of the bank group addressing, is placed as the least significant user address bit of the HBM memory map (addr[5]). With the default address map, an AXI transaction with an AxLEN of 0x1 and AxADDR of 0x0 executes two discrete commands on the HBM interface. The first goes to Row 0, Bank Group 0, Bank address 0, Column 0. The second goes to Row 0, Bank Group 1, Bank address 0, and Column 0.

Having the Bank Group Interleave option with BG0 as the least significant bit is in service of sequential memory accesses. It decreases the amount of time spent waiting for protocol execution because the controller splits the accesses between two banks in two separate bank groups. An AXI transaction with an AxLEN of 0x1 demonstrates this behavior, but fully leveraging these concepts for higher efficiency requires more consideration with longer transaction lengths or leveraging traffic streams mapped to bank addresses across bank groups.

The default address map option, RAx-SID (for certain devices)-BAx-BG1-CAx-BG0, is ideal for traffic with linear and random block accesses. An example of a random block access would be where the master is accessing the first 512 bytes of a randomly selected, 4 KB aligned address. The bank group interleaving alleviates some of the protocol exposure for bigger AXI lengths. The IP allows custom address mapping for different types of accesses. The user defined address map allows the row, bank, and column bits to be placed in the desired locations.

The Row Bank Column address map without bank group interleaving works best when the traffic is accessing the addresses randomly. Thus, in any of the Routing Use Cases and HBM Subsystems where the master is randomly accessing the memory, the Row Bank Column would be the preferred address mapping.