Address Mapping Notation - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The notation system used in this document is explained in the following example.

A certain DRAM component has the following properties:
  • 16 row address bits (64K rows per bank)
  • 10 column address bits (1024 columns per row)
  • 2 bank address bits (4 banks per bank group)
  • 2 bank group address bits (4 bank groups)
The DRAM bus width is 64 bits. The basic DRAM access unit is 64 bytes. The desired address mapping is:
  • System_addr[2:0] is not used by the DRAM due to the 64-bit width
  • Column_addr[9:0] = system_addr[12:3]
  • Bank_group_addr[1:0] = system_addr[14:13]
  • Bank_addr[2:0] = system_addr[16:15]
  • Row_addr[15:0] = system_addr[32:17]

The notation for this mapping is: 16R-2B-2BG-10C.

Figure 1. Example Address Mapping