Address Parity Error Injection - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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A parity error can be injected on the DRAM Command/Address bus using the add_par_err_inj register. This register contains fields to inject a parity error on each DDRMC sub-channel. The injector can be set up to pick a Read CAS command, a Write CAS command, or a random command. The register logs the command the error was injected on and sets a “done” bit. After an error inject event occurs, the “done” bit can be cleared and the error injector can be re-enabled to inject another error.

  1. Select the type of command for error injection by writing to DDRMC_MAIN_n.add_par_err_inj[cmd_type{0,1}], where n represents the DDRMC number, and the 0 or 1 after cmd_type represents the DDRMC sub-channel number. By default, errors are injected on any DRAM command. Setting this register to 1 limits error injection to DRAM Read CAS commands, and setting it to 2 limits error injection to DRAM Write CAS commands.
  2. Enable error injection by writing 1’b1 to DDRMC_MAIN_n.add_par_err_inj[cmd_en{0,1}].
  3. Access memory with the selected command type.
  4. Read DDRMC_MAIN_n.add_par_err_inj[cmd_done{0,1}]. A value of 1’b1 indicates that error injection is done. The dram_rank{0,1} and dram_cmd{0,1} fields can be read to see which command and rank had an error injected.
  5. Read DDRMC_MAIN_n.DDRMC_ISR[DRAM_PARITYm] to look for the DRAM Parity Error status. n = the memory controller number, and m = the channel number within a given memory controller.