Address Re-mapping - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The NMU supports address remapping as a way to override the default address map as well as to provide simple address virtualization. There are sixteen sets of address remap registers in the configuration space of the NMU. Each address remap register supports:

  • Matching address ranges from 64 KB to the full address map;
  • Address matching to determine the destination ID to route the transaction;
  • Optional replacement address for the matched portion of the address.

Use Cases for Address Remapping

PL to PL Remapping
If a PL Master only supports 32-bit addressing, by using the NoC remapping feature a 32-bit address can be translated to access PL endpoints in the address region 0x200_0000_0000. This use case is illustrated in the following figure.
Figure 1. PL to PL

Table 1. Remapping
Input Address Remapped Address
0x0000_0000 0x200_0000_0000
0x0000_0001 0x200_0000_0001
0x0000_0002 0x200_0000_0002
... ...
0xFFFF_FFFF 0x200_FFFF_FFFF
PL to DDRMC Remapping
  • Similar to the previous example, a PL Master with 32-bit addressing can access a DDR MC memory range by using NoC remapping. This use case is illustrated in the following figure.
    Figure 2. PL to DDRMC

    As shown in the previous figure, to perform memory remapping, the first NoC would remap the 32-bit address to the desired space and, through an INI connection in the second NoC, be written to memory.

Note: Although CIPS to DDRMC re-mapping is theoretically possible, it is strongly discouraged because there are no NoC address ranges between 0x8000_0000-0xFFFF_FFFFF in system address space that the R5 can borrow from to get additional DDRMC memory range.