Addressing - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The NoC supports a rich set of addressing mechanisms. Every configured NMU and NSU in a design is assigned a unique 12-bit ID referred to as the destination ID (destID). When a packet arrives at an input port of a NoC packet switch (NPS) the destID and the virtual channel number of the packet are used to look in the routing tables to find the output port to send the packet. The output port determines the next segment of the route, delivering the packet to the next NPS or NMU/NSU.

An NMU in AXI4 mode can be configured to use one of four strategies to determine the destID. These strategies in order of precedence are:

Fixed DestID
A configuration register in the NMU can be programmed to contain a single destination ID. When enabled, the programmed value specifies the destination for all memory mapped transactions originating from that NMU, regardless of address.
User-defined DestID
User logic in the PL region might drive the destination ID onto the destination interface pins of the NMU. This ID is then used to route the memory mapped transaction to the destination. Separate destination interface pins are provided for read and write transactions. This feature is not supported in the current release of Vivado.
Address remap
The NMU supports an address remapping mechanism to override the default address map, provide a programmed destination ID, and support simple address virtualization.
Address decode
The NMU may decode the physical address of the AXI transaction to determine the destination ID of the addressed resource. The NMU contains a set of address decoders and associated programmable registers to allow transactions destined for different regions of the physical address space to be mapped to preprogrammed destIDs.