Clocking - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

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1.0 English

The HBM Controller may be clocked from an internal clock sourced by CIPS (HSM0 of the HBM SLR), or from dedicated clock pins in the same IO bank as the HBM (800 and 801). Based on the input clock frequency provided and the desired operation rate of the HBM, the dedicated PLL will be automatically configured to match the requirements.

The dedicated clock pair are C4CCIO_PAD0 and _PAD1. C4CCIO_PAD0 is the P-side and _PAD1 is the N-side of the LVDS differential pair. When used as single ended, the clock should be connected to C4CCIO_PAD0 and configured as LVCMOS12.

Refer to the Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960) for information on supported data rates.