Configuring the HBM PHYIO Control IP - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2023-11-01
Version
1.0 English

The AXI NoC IP supports configuring only contiguous HBM memory channels. To enable non-contiguous memory channels, it is necessary to instantiate more than one instance of the AXI NoC IP. Each instance of the AXI NoC IP can enable the desired memory channels. As the HBM PHY logic is shared across an entire stack, it is necessary to instantiate the HBM PHYIO Control Block outside of the NoC, to avoid duplication among the multiple axi_noc instances. The HBM PHYIO Control IP is to be used in such situations.

For example, a design has two instances of the AXI NoC IP. In the first instance, HBM Channel 0 of Stack 0 is enabled.

Figure 1. HBM Channel 0 of Stack 0 Enabled

In the second AXI NoC IP instance, HBM Channel 2 of Stack 0 is enabled.

Figure 2. HBM Channel 2 of Stack 0 Enabled

In such a case, the HBM PHYIO Control IP must be instantiated, and configured to select the appropriate channels (in this example, Channel 0 and Channel 1) of the corresponding stack (in this example, Stack 0) to enable the hbm_phyio_control block. The IP will instantiate the necessary logic for the selected channels.

Figure 3. Channel 0 and Channel 2 from Stack 0 selected in the HBM PHYIO Control IP

Make sure the HBM Memory Frequency and the HBM Reference Frequency is the same across the AXI NoC IPs and the HBM PHYIO Control IP. After the instantiation of the IPs, connect the HBM_PHYIO ports of the HBM PHYIO Control IP to the respective HBM_PHYIO ports of the AXI NoC IP.

The following figure shows the connections between the HBM PHYIO Control IP and the AXI NoC IPs.

Figure 4. Block Design with HBM PHYIO Control IP